These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear
(CLR) input. The gated serial (A and B) inputs permit complete control over
incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop
to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which
then determines the state of the first flip-flop. Data at the serial inputs can be changed while
CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the
low-to-high-level transition of CLK.
- Wide Operating Voltage Range of 2 V to 6 V
- Outputs Can Drive Up to 10 LSTTL Loads
- Low Power Consumption, 80-µA Maximum ICC
- Typical tpd = 20 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1-µA Maximum
- AND-Gated (Enable/Disable) Serial Inputs
- Fully Buffered Clock and Serial Inputs
- Direct Clear
- On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include
Testing of All Parameters.
| Configuration | Serial-in, Parallel-out |
| Bits (#) | 8 |
| Technology family | HC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 6 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock frequency (MHz) | 24 |
| IOL (max) (mA) | 5.2 |
| IOH (max) (mA) | -5.2 |
| Supply current (max) (µA) | 160 |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Space |