PGA112 Texas instruments

PGA112

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PGA112

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Описание

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package. All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

Rail-to-Rail Input and Output
Offset: 25 µV (Typical), 100 µV
(Maximum)
Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
(Maximum)
Low Noise: 12 nV/√Hz
Input Offset Current: ±5 nA Maximum (25°C)
Gain Error: 0.1% Maximum (G ≥ 32),
0.3% Maximum (G > 32)
Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
PGA116)
Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
(PGA113, PGA117)
Gain Switching Time: 200 ns
2 Channel MUX: PGA112, PGA113
10 Channel MUX: PGA116, PGA117
Four Internal Calibration Channels
Amplifier Optimized for Driving CDAC ADCs
Output Swing: 50 mV to Supply Rails
AV_DD and DV_DD for Mixed Voltage Systems
I_Q = 1.1 mA (Typical)
Software and Hardware Shutdown: I_Q ≤ 4 µA
(Typical)
Temperature Range: –40°C to 125°C
SPI™ Interface (10 MHz) With Daisy-Chain
Capability

PGA/VGA	PGA
Number of channels	2
BW at Acl (MHz)	10
Vs (max) (V)	5.5
Vs (min) (V)	2.2
Acl, min spec gain (V/V)	1
Gain (max) (dB)	42
Slew rate (typ) (V/µs)	3
Operating temperature range (°C)	-40 to 125
Features	Small Size
Rating	Catalog