These triple 3-input positive-nor gates are designed for 2-V to 5.5-V VCC operation.
The 'LV27A devices perform the Boolean function Y = (A + B + C)\ or Y = A\ B\ C\ in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
- 2-V to 5.5-V VCC Operation
- Max tpd of 7 ns at 5 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
| Technology family | LV-A |
| Number of channels | 3 |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 5.5 |
| Inputs per channel | 3 |
| IOL (max) (mA) | 12 |
| IOH (max) (mA) | -12 |
| Output type | Push-Pull |
| Input type | Standard CMOS |
| Features | Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Data rate (max) (MBits) | 70 |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |