ADS54J54 Texas instruments

ADS54J54

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ADS54J54

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Описание

The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.

4 Channel, 14-Bit 500 MSPS ADC
Analog input buffer with high impedance input
Flexible input clock buffer with divide by 1/2/4
1.25 V_PP Differential full-scale input
JESD204B Serial interface
- Subclass 1 compliant up to 5 Gbps
- 1 Lane Per ADC up to 250 Msps
- 2 Lanes Per ADC up to 500 Msps
64-Pin QFN Package (9 mm x 9 mm)
Key specifications:
- Power dissipation: 875 mW/ch
- Input bandwidth (3 dB): 900 MHz
- Aperture jitter: 98 fs rms
- Channel isolation: 85 dB
- Performance at ƒ_in = 170 MHz at 1.25 V_PP,
  1lane 2x Decimation –1 dBFS
  - SNR: 67.2 dBFS
  - SFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3
- Performance at ƒ_in = 370 MHz at 1.25 V_PP,
  2lane no Decimation –1 dBFS
  - SNR: 64.7 dBFS
  - SFDR: 75 dBc HD2,3; 83 dBFS non-HD2,3

Sample rate (max) (Msps)	500
Resolution (Bits)	14
Number of input channels	4
Interface type	JESD204B
Analog input BW (MHz)	900
Features	High Performance
Rating	Catalog
Peak-to-peak input voltage range (V)	1.25
Power consumption (typ) (mW)	3500
Architecture	Pipeline
SNR (dB)	68.3
ENOB (Bits)	11
SFDR (dB)	95
Operating temperature range (°C)	-40 to 85
Input buffer	Yes