ADC34J42 Texas instruments

ADC34J42

Уточнить цену

ADC34J42

Уточнить цену

СРАВНИТЬ

В СРАВНЕНИИ

Уточнить цену

Описание

The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.

Quad Channel
14-Bit Resolution
Single 1.8-V Supply
Flexible Input Clock Buffer with Divide-by-1, -2, -4
SNR = 72 dBFS, SFDR = 86 dBc at
f_IN = 70 MHz
Ultra-Low Power Consumption:
- 203 mW/Ch at 160 MSPS
Channel Isolation: 105 dB
Internal Dither
JESD204B Serial Interface:
- Supports Subclass 0, 1, 2
- Supports One Lane per ADC up to 160 MSPS
Support for Multi-Chip Synchronization
Pin-to-Pin Compatible with 12-Bit Version
Package: VQFN-48 (7 mm × 7 mm)

Sample rate (max) (Msps)	50
Resolution (Bits)	14
Number of input channels	4
Interface type	JESD204B
Analog input BW (MHz)	450
Features	Low Power
Rating	Catalog
Peak-to-peak input voltage range (V)	2
Power consumption (typ) (mW)	491
Architecture	Pipeline
SNR (dB)	72.8
ENOB (Bits)	11.9
SFDR (dB)	93
Operating temperature range (°C)	-40 to 85
Input buffer	No