ADC32J23 Texas instruments

ADC32J23

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ADC32J23

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Описание

The ADC32J2x is a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

Dual Channel
12-Bit Resolution
Single 1.8-V Supply
Flexible Input Clock Buffer with Divide-by-1, -2, -4
SNR = 70.3 dBFS, SFDR = 88 dBc at
f_IN = 70 MHz
Ultralow Power Consumption:
- 227 mW/Ch at 160 MSPS
Channel Isolation: 105 dB
Internal Dither
JESD204B Serial Interface:
- Subclass 0, 1, 2 Compliant up to 3.2 Gbps
- Supports One Lane per ADC up to 160 MSPS
Support for Multichip Synchronization
Pin-to-Pin Compatible with 14-Bit Version
(ADC32J4X)
Package: VQFN-48 (7 mm × 7 mm)

Sample rate (max) (Msps)	80
Resolution (Bits)	12
Number of input channels	2
Interface type	JESD204B
Analog input BW (MHz)	450
Features	Low Power
Rating	Catalog
Peak-to-peak input voltage range (V)	2
Power consumption (typ) (mW)	329
Architecture	Pipeline
SNR (dB)	70.4
ENOB (Bits)	11.4
SFDR (dB)	96
Operating temperature range (°C)	-40 to 85
Input buffer	No