ADC12DJ3200QML-SP Texas instruments

ADC12DJ3200QML-SP

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ADC12DJ3200QML-SP

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Описание

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 7 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

ADC core:
- 12-Bit resolution
- Up to 6.4 GSPS in single-channel mode
- Up to 3.2 GSPS in dual-channel mode
Noise floor (no signal, V_FS = 1 V_PP-DIFF):
- Dual-channel mode: –149.5 dBFS/Hz
- Single-channel mode: –152.4 dBFS/Hz
Peak noise power ratio (NPR): 45.4 dB
Buffered analog inputs with V_CMI of 0 V:
- Analog input bandwidth (–3 dB): 7 GHz
- Usable input frequency range: >10 GHz
- Full-scale input voltage (V_FS, default): 0.8 V_PP
Noiseless aperture delay (t_AD) adjustment:
- Precise sampling control: 19-fs step size
- Temperature and voltage invariant delays
Easy-to-use synchronization features
- Automatic SYSREF timing calibration
- Timestamp for sample marking
JESD204B subclass-1 compliant interface:
- Maximum lane rate: 12.8 Gbps
- Up to 16 lanes allows reduced lane rate
Digital down-converters in dual-channel mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
Radiation performance:
- Total Ionizing Dose (TID): 300 krad (Si)
- Single Event Latchup (SEL): 120 MeV-cm²/mg
- Single Event Upset (SEU) immune registers
Power consumption: 3 W

Sample rate (max) (Msps)	3200, 6400
Resolution (Bits)	12
Number of input channels	1, 2
Interface type	JESD204B
Analog input BW (MHz)	7300
Features	Ultra High Speed
Rating	Space
Peak-to-peak input voltage range (V)	0.8
Power consumption (typ) (mW)	3000
Architecture	Folding Interpolating
SNR (dB)	57.2
ENOB (Bits)	8.9
SFDR (dB)	76
Operating temperature range (°C)	-55 to 125, 25 to 25
Input buffer	Yes
Radiation, TID (typ) (krad)	300
Radiation, SEL (MeV·cm2/mg)	120