ADC12DJ3200 Texas instruments

ADC12DJ3200

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ADC12DJ3200

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Описание

The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

ADC core:
- 12-bit resolution
- Up to 6.4 GSPS in single-channel mode
- Up to 3.2 GSPS in dual-channel mode
Performance specifications:
- Noise floor (no signal, V_FS = 1.0 V_PP-DIFF):
  - Dual-channel mode: –151.8 dBFS/Hz
  - Single-channel mode: –154.6 dBFS/Hz
- HD2, HD3: –65 dBc up to 3 GHz
Buffered analog inputs with V_CMI of 0 V:
- Analog input bandwidth (–3 dB): 8.0 GHz
- Usable input frequency range: >10 GHz
- Full-scale input voltage (V_FS, default): 0.8 V_PP
- Analog input common-mode (V_ICM): 0 V
Noiseless aperture delay (T_AD) adjustment:
- Precise sampling control: 19-fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
JESD204B serial data interface:
- Supports subclass 0 and 1
- Maximum lane rate: 12.8 Gbps
- Up to 16 lanes allows reduced lane rate
Digital down-converters in dual-channel mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
- Four independent 32-Bit NCOs per DDC
Power consumption: 3 W
Power supplies: 1.1 V, 1.9 V

Sample rate (max) (Msps)	3200, 6400
Resolution (Bits)	12
Number of input channels	1, 2
Interface type	JESD204B
Analog input BW (MHz)	8000
Features	Ultra High Speed
Rating	Catalog
Peak-to-peak input voltage range (V)	0.8
Power consumption (typ) (mW)	3000
Architecture	Folding Interpolating
SNR (dB)	57.6
ENOB (Bits)	9
SFDR (dB)	75
Operating temperature range (°C)	-40 to 85
Input buffer	Yes