The ADC12D1620QML uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling power-saving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.
- Total ionizing dose (TID) to 300 krad(Si)
- Single event functional interrupt (SEFI) tested
- Single event latch-up (SEL) > 120 MeV-cm2/mg
- Cold sparing capable
- Wide temperature range –55°C to +125°C
- Power consumption = 3.8 W or 2.7 W (1600- or 800-MHz clock)
- 3-dB Input bandwidth = 3 GHz
- Low-sampling power-saving mode (LSPSM) reduces power consumption and improves performance for fCLK ≤ 800 MHz
- Auto-sync function for multi-chip systems
- Time stamp feature to capture external trigger
- Test patterns at output for system debug
- 1:1 Non-demuxed or 1:2 or 1:4 parallel demuxed LVDS outputs
- Single 1.9-V power supply
| Sample rate (max) (Msps) | 1600, 3200 |
| Resolution (Bits) | 12 |
| Number of input channels | 1, 2 |
| Interface type | Parallel LVDS |
| Analog input BW (MHz) | 2400 |
| Features | Ultra High Speed |
| Rating | Space |
| Peak-to-peak input voltage range (V) | 0.8 |
| Power consumption (typ) (mW) | 3880 |
| Architecture | Folding Interpolating |
| SNR (dB) | 59.8 |
| ENOB (Bits) | 9.5 |
| SFDR (dB) | 67.4 |
| Operating temperature range (°C) | -55 to 125, 25 to 25 |
| Input buffer | Yes |
| Radiation, TID (typ) (krad) | 300 |
| Radiation, SEL (MeV·cm2/mg) | 120 |