The SN74LV1T125 is a single buffer gate with reduced input thresholds to support voltage translation applications.
- Single-supply voltage translator at 5-V, 3.3-V, 2.5-V, and 1.8-V VCC
- Operating range of 1.8 V to 5.5 V
- Up translation:
- 1.2 V(1) to 1.8 V at 1.8-V VCC
- 1.5 V(1) to 2.5 V at 2.5-V VCC
- 1.8 V(1) to 3.3 V at 3.3-V VCC
- 3.3 V to 5.0 V at 5.0-V VCC
- Down translation:
- 3.3 V to 1.8 V at 1.8-V VCC
- 3.3 V to 2.5 V at 2.5-V VCC
- 5.0 V to 3.3 V at 3.3-V VCC
- Logic output is referenced to VCC
- Output drive:
- 8.0 mA output drive at 5 V
- 7.0 mA output drive at 3.3 V
- 3.0 mA output drive at 1.8 V
- Characterized up to 50 MHz at 3.3-V VCC
- 5.0 V Tolerance on input pins
- –40°C to 125°C operating temperature range
- Latch-Up Performance Exceeds 250 mAPer JESD 17
- Supports standard logic pinouts
- CMOS output B compatible with AUP1G and LVC1G families (1)
(1)Refer to the VIH/VIL and output drive for lower VCC condition.
| Technology family | LV1T |
| Applications | GPIO, I2S, UART |
| Bits (#) | 1 |
| Configuration | 1 Ch A to B 0 Ch B to A |
| High input voltage (min) (V) | 1 |
| High input voltage (max) (V) | 5.5 |
| Vout (min) (V) | 0 |
| Vout (max) (V) | 5.5 |
| Data rate (max) (MBits) | 100 |
| IOH (max) (mA) | -8 |
| IOL (max) (mA) | -8 |
| Supply current (max) (µA) | 5.5 |
| Features | 4.2, 4.64 |
| Input type | TTL-Compatible CMOS |
| Output type | 3-State, Balanced CMOS |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 125 |