The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the
CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear
voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A
signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled
(with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a passive low-pass filter, the
SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of
linear operational amplifier techniques. Various applications include telecommunications, digital
phase-locked loop and signal generators.
- ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
- Choice of Three Phase Comparators
- Exclusive OR
- Edge-Triggered J-K Flip-Flop
- Edge-Triggered RS Flip-Flop
- Excellent VCO Frequency Linearity
- VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
- Optimized Power-Supply Voltage Range From 3 V to 5.5 V
- Wide Operating Temperature Range From –40°C to +125°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
| Technology family | LV-A |
| Bits (#) | 1 |
| Supply voltage (min) (V) | 3 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Supply current (max) (µA) | 50 |
| IOL (max) (mA) | 12 |
| IOH (max) (mA) | -12 |
| Operating temperature range (°C) | -40 to 85 |
| Rating | Catalog |