Information at the data (D) inputs meeting the setup time requirements is transferred to
the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a
particular voltage level and is not related directly to the transition time of the positive-going
pulse. When CLK is at either the high or low level, the D input has no effect at the output.
- Wide Operating Voltage Range
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption
- Typical tpd = 12 ns
- Low Input Current
- Contain Eight Flip-Flops With
Single-Rail Outputs - Direct Clear Input
- Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
| Technology family | HC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 6 |
| Input type | CMOS |
| Output type | CMOS |
| IOL (max) (mA) | 5.2 |
| IOH (max) (mA) | -5.2 |
| Operating temperature range (°C) | 25 to 25 |
| Rating | Space |