CDCL1810A Texas instruments

CDCL1810A

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CDCL1810A

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Описание

The CDCL1810A is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN/P, where P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80. The CDCL1810A supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled. With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810A can support a single-ended clock input as outlined in Pin Configuration and Functions. All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only. The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810A is available in a 48-pin QFN (RGZ) package.

othersSingle 1.8 V Supply
High-Performance Clock Distributor with 10 Outputs
Low Input-to-Output Additive Jitter: as low as 10fs RMS
Low-Voltage Differential Signaling (LVDS) Input, 100Ω
Differential On-Chip Termination, up to 650 MHz Frequency
Differential Current Mode Logic (CML) Outputs, 50Ω
Single-Ended On-Chip Termination, up to 650 MHz Frequency
Two Groups of Five Outputs Each with Independent Frequency
Division Ratios
Output Frequency Derived with Divide Ratios of 1, 2, 4, 5,
8, 10, 16, 20, 32, 40, and 80
Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements
Power Consumption: 410 mW Typical
Output Enable Control for Each Output
SDA/SCL Device Management Interface
48-pin VQFN (RGZ) Package
Industrial Temperature Range: –40°C to +85°C

Function	Clock buffer, Clock divider
Additive RMS jitter (typ) (fs)	40
Output frequency (max) (MHz)	650
Number of outputs	10
Output supply voltage (V)	1.8
Core supply voltage (V)	1.8
Output skew (ps)	64
Features	I2C interface
Operating temperature range (°C)	-40 to 85
Rating	Catalog
Output type	CML
Input type	LVDS